In the formation of a Field-Effect Transistor (FinFET), a semiconductor fin is formed first, followed by forming a gate stack on a portion of the semiconductor fin. The exposed end portions of the fin on opposite sides of the gate stack are removed to form recesses. Source and drain regions are then re-grown in the recesses through epitaxy.
The performance of Field-Effect Transistors (FinFETs) is strongly affected by the profiles of source and drain regions, which profiles include, for example, the degree of undercut, which is how much the recesses extend under the gate stack. To maintain a controllable performance, it is desired that the magnitude of the undercuts can be controlled accurately. Furthermore, it is desirable that the undercuts are uniform throughout the same type of FinFETs on the same chip. The undercut control, however, is difficult to achieve. For example, due to the pattern loading effect caused by the pattern density of the exposed fin portions, the undercuts may vary significantly. Controlling the undercuts thus becomes a challenge.